The present invention relates to a semiconductor apparatus and in particular to a semiconductor apparatus including a semiconductor chip over which an amplifier circuit for amplifying high-frequency signals is formed.
Radio signal systems include an amplifier circuit for handling high-frequency signals in a microwave band. Among examples of such an amplifier circuit is a field-effect transistor (FET) including a GaAs substrate. Such an FET including a GaAs substrate will be referred to as a GaAsFET. A semiconductor apparatus that handles such high-frequency signals requires a technology that reduces a parasitic capacitance related to a semiconductor chip to improve high-frequency characteristics. Technologies for reducing a parasitic capacitance attributable to a package are disclosed in Japanese Patent No. 3132449 and Japanese Unexamined Patent Publication No. Hei 5 (1993)-218231. These technologies reduce a parasitic capacitance adjacent to a semiconductor chip to improve high-frequency characteristics, by incorporating a GaAsFET into a hollow package.
Japanese Patent No. 3132449 also discloses as a second embodiment a technology that incorporates a semiconductor chip and an external device associated with the semiconductor chip into a single package. Another example of such an embodiment is disclosed in Japanese Unexamined Patent Publication No. Sho 63 (1988)-132459. In a semiconductor apparatus disclosed in Japanese Unexamined Patent Publication No. Sho 63 (1988)-132459, a bypass capacitor disposed is disposed below a semiconductor chip and between a ground terminal and a power supply terminal for supplying power to a circuit formed over the semiconductor chip. The bypass capacitor is interposed between lead frames.
In the meantime, where an FET is used to form an amplifier circuit for amplifying high-frequency signals, the FET is used to form a source ground circuit. At this time, the FET is formed over a semiconductor chip and coupled to an external circuit via a bonding wire and a lead frame. For this reason, inductance components attributable to the bonding wire and the lead frame are added to the terminals of the mounted FET as parasitic components. Such inductance components have high impedance in a high-frequency band and therefore would cause a reduction in the amplification factor of the amplifier circuit in a high-frequency band. For this reason, there is a need for a technology that reduces the impedance of a ground terminal for handling high-frequency signals. Examples of a semiconductor apparatus for handling high-frequency signals are disclosed in Japanese Patent Nos. 3328542, 3612268, and 3825874.
These technologies form a series resonant circuit for reducing inductance components of the source (ground electrode) of an FET. Using the series resonant circuit, the technologies reduce the impedance of the source terminal of the FET in a high-frequency band to improve high-frequency characteristics.